目录
全加器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add is
port(
a, b: in std_logic_vector(3 downto 0);
c: in std_logic;
sum: out std_logic_vector(3 downto 0);
cout: out std_logic
);
end add;
architecture arc of add is
signal sumt: std_logic_vector(4 downto 0);
begin
sumt <= ('0'&a) + b + c;
cout <= sumt(4);
sum <= sumt(3 downto 0);
end arc;
四输入与门
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and_gate is
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
d: in std_logic;
result: out std_logic
);
end and_gate;
architecture arc of and_gate is
begin
result <= a and b and c and d;
end arc;
Y=AB+CD+EF
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and_gate is
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
d: in std_logic;
e: in std_logic;
f: in std_logic;
result: out std_logic
);
end and_gate;
architecture arc of and_gate is
begin
result <= (a and b) or (c and d) or (e and f);
end arc;
3-8 译码器
这里我写的是解码出正的，实际上应该是反的。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port (
inp: in std_logic_vector(2 downto 0);
outp: out std_logic_vector(7 downto 0)
);
end decoder;
architecture dec_behavior of decoder is
begin
outp(0) <= '1' when inp = "000" else '0';
outp(1) <= '1' when inp = "001" else '0';
outp(2) <= '1' when inp = "010" else '0';
outp(3) <= '1' when inp = "011" else '0';
outp(4) <= '1' when inp = "100" else '0';
outp(5) <= '1' when inp = "101" else '0';
outp(6) <= '1' when inp = "110" else '0';
outp(7) <= '1' when inp = "111" else '0';
end dec_behavior;
8-3 编码器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port (
inp: in std_logic_vector(2 downto 0);
outp: out std_logic_vector(7 downto 0)
);
end decoder;
architecture dec_behavior of decoder is
begin
outp(0) <= '0' when inp = "000" else '1';
outp(1) <= '0' when inp = "001" else '1';
outp(2) <= '0' when inp = "010" else '1';
outp(3) <= '0' when inp = "011" else '1';
outp(4) <= '0' when inp = "100" else '1';
outp(5) <= '0' when inp = "101" else '1';
outp(6) <= '0' when inp = "110" else '1';
outp(7) <= '0' when inp = "111" else '1';
end dec_behavior;Gray 码转换为二进制码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gray_encoder is
port (
outp: out std_logic_vector(3 downto 0);
inp: in std_logic_vector(3 downto 0)
);
end gray_encoder;
architecture enc_behavior of gray_encoder is
begin
outp(3) <= inp(3);
outp(2) <= inp(3) xor inp(2);
outp(1) <= inp(3) xor inp(2) xor inp(1);
outp(0) <= inp(3) xor inp(2) xor inp(1) xor inp(0);
end enc_behavior;
38 译码器（含使能端）
为什么所有喜欢的东西，一旦变成了强制的作业，就会让我恐惧想要逃离……
设计思路
接口有：三个使能端（两个0有效，一个1有效）。三个都有效的时候进行译码。根据输入的三个地址进行译码，译码结果是反过来的。
VHDL 代码
library ieee;
use ieee.std_logic_1164.all;
entity decoder38 is
port(
e1, e2, e3 : in std_logic;
a : in std_logic_vector(2 downto 0);
y : out std_logic_vector(0 to 7)
);
end decoder38;
architecture decoder38Arch of decoder38 is
begin
process(e1, e2, e3, a)
begin
if(e1 = '1' and e2 = '0' and e3 = '0') then
case a is
when "000" => y <= "10000000";
when "001" => y <= "01000000";
when "010" => y <= "00100000";
when "011" => y <= "00010000";
when "100" => y <= "00001000";
when "101" => y <= "00000100";
when "110" => y <= "00000010";
when "111" => y <= "00000001";
when others => y <= "11111111";
end case;
else
y <= "11111111";
end if;
end process;
end decoder38Arch;运行结果
8421 加法计数器
设计思路
接口有：时钟，清零，和四位输出。
当前一个脉冲为 1001 时，输出脉冲为 0000。
VHDL 代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter8421 is
port(
clock : in std_logic;
clear : in std_logic;
y : out std_logic_vector(3 downto 0)
);
end counter8421;
architecture counter8421Arch of counter8421 is
signal temp : std_logic_vector(3 downto 0) := "0000";
begin
process(clock, clear)
begin
if(clear = '0') then
temp <= "0000";
y <= temp;
elsif (clock'event and clock = '1') then
if (temp = "1001") then
temp <= "0000";
y <= temp;
else
temp <= temp + 1;
y <= temp;
end if;
end if;
end process;
end counter8421Arch;运行结果
可逆计数器
设计一个 3 位格雷码可逆计数器，$y=1, 0$ 分别表示加减。
设计思路
三位的话状态不是特别多，可以穷举。
VHDL 代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity greyCounter is
port(
clock : in std_logic;
clear : in std_logic;
y : in std_logic; -- 1: plus, 0: minus
q : out std_logic_vector(2 downto 0)
);
end greyCounter;
architecture greyCounterArch of greyCounter is
signal temp : std_logic_vector(2 downto 0);
begin
process(clock, clear, y)
begin
if(clear = '0') then
temp <= "000";
elsif (clock'event and clock = '1') then
if (y = '1') then
case temp is
when "000" => temp <= "001";
when "001" => temp <= "011";
when "011" => temp <= "010";
when "110" => temp <= "111";
when "111" => temp <= "101";
when "101" => temp <= "100";
when "100" => temp <= "000";
when others => temp <= "000";
end case;
elsif (y = '0') then
case temp is
when "000" => temp <= "100";
when "100" => temp <= "101";
when "101" => temp <= "111";
when "111" => temp <= "110";
when "110" => temp <= "010";
when "010" => temp <= "011";
when "011" => temp <= "001";
when others => temp <= "000";
end case;
else
temp <= "000";
end if;
end if;
q <= temp;
end process;
end greyCounterArch;运行结果
有限状态机
设计思路
通过一个整数变量表示状态，然后按照条件跳转。和计数器应该差不多吧。
VHDL 代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fsm is
port(
clock : in std_logic;
k : in std_logic;
q : out integer range 0 to 3
);
end fsm;
architecture fsmArch of fsm is
signal temp : integer range 0 to 3;
begin
process(clock, k)
begin
if (clock'event and clock = '1') then
if (k = '1') then
case temp is
when 0 => temp <= 0;
when 1 => temp <= 2;
when 2 => temp <= 2;
when 3 => temp <= 0;
when others => temp <= 0;
end case;
elsif (k = '0') then
case temp is
when 0 => temp <= 1;
when 1 => temp <= 1;
when 2 => temp <= 3;
when 3 => temp <= 3;
when others => temp <= 0;
end case;
else
temp <= 0;
end if;
end if;
q <= temp;
end process;
end fsmArch;运行结果
